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nathalies fpl_paper [21 articles]

Neue Publikationen in nathalies Bibliothek eingetragen unter dem Bezeichner: fpl_paper. You can also see everyone's fpl_paper.
  • Power-aware Technology Mapping for LUT-based FPGAs
    Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on (2002), pp. 211-218.
    by JH Anderson, FN Najm
    posted to activity algorithms for_thesis fpl_paper fpt_paper logic_synthesis lut power power_estimation probability technology_mapping xilinx by nathalie on 2006-09-01 06:55:25 as ** along with 1 person ceegrs2
  • Dynamic Voltage Scaling for Commercial FPGAs
    Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology (2005), pp. 173-180.
    by CT Chow, LSM Tsui, PHW Leong, W Luk, SJE Wilton
    posted to altera architecture for_thesis fpga fpl_paper fpt_paper power power_estimation vlsi xilinx by nathalie on 2006-09-01 06:46:27 as ** along with 2 people reactgary ceegrs2
  • Transition density: a new measure of activity in digital circuits
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 12, No. 2. (1993), pp. 310-323.
    by FN Najm
    posted to activity for_thesis fpl_paper fpt_paper power_estimation printed transition_density vlsi by nathalie on 2006-07-06 19:31:29 as **
  • The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
    (August 2004), pp. 719-728.
    by SJE Wilton, SS Ang, W Luk
    posted to for_thesis fpga fpl_paper pipelined power by nathalie on 2006-06-26 23:10:49 as ** along with 1 person ceegrs2
  • Activity Estimation For Field-Programmable Gate Arrays
    (August 2006)
    by J Lamoureux, SJE Wilton
    posted to activity for_thesis fpl_paper fpt_paper power_estimation by nathalie on 2006-06-23 18:26:30 as ***
  • SIS: A system for sequential circuit synthesis
    (1992)
    by EM Sentovich, KJ Singh, L Lavagno, C Moon, R Murgai, A Saldanha, H Savoj, PR Stephan, RK Brayton, Sangiovanni A Vincentelli
    posted to for_thesis fpl_paper fpt_paper logic_synthesis synthesis vlsi by nathalie on 2006-06-20 23:21:57 as **
  • Information theoretic measures for power analysis [logic design]
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 15, No. 6. (1996), pp. 599-610.
    by D Marculescu, R Marculescu, M Pedram
    posted to for_thesis fpl_paper power power_estimation printed by nathalie on 2006-03-11 07:01:07 as **
  • High-Level Power Analysis and Optimization
    (June 1997)
    by Anand Raghunathan
    posted to fpl_paper power power_estimation synthesis by nathalie on 2006-03-11 06:06:26 as **
  • High-Level Power Analysis and Optimization
    (30 November 1997)
    by Anand Raghunathan, Niraj K Jha, Sujit Dey
    posted to for_thesis fpl_paper power power_estimation synthesis by nathalie on 2006-03-11 05:49:23 as **
  • Architectural power analysis: The dual bit type method
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 3, No. 2. (1995), pp. 173-187.
    by PE Landman, JM Rabaey
    posted to adder architecture arithmetic for_thesis fpl_paper multiplier power power_estimation printed by nathalie on 2006-03-05 02:24:58 as read along with 1 person ceegrs2
  • A verilog RTL synthesis tool for heterogeneous FPGAs
    Field Programmable Logic and Applications, 2005. International Conference on (2005), pp. 305-310.
    by P Jamieson, J Rose
    posted to altera arithmetic coarse_grained_architectures dsp for_thesis fpga fpl_paper logic_synthesis printed synthesis technology_mapping by nathalie on 2006-02-19 21:11:59 as read
  • Embedded Floating-Point Units in FPGAs
    (2006), pp. 12-20.
    by Michael J Beauchamp, Scott Hauck, Keith D Underwood, Scott K Hemmert
    posted to arithmetic floating_point for_thesis fpga fpl_paper printed by nathalie on 2006-02-17 20:21:15 as **
  • An FPGA architecture with enhanced datapath functionality
    (2003), pp. 195-204.
    by Katarzyna Leijten-Nowak, Jef L van Meerbergen
    posted to architecture arithmetic dsp for_thesis fpga fpl_paper printed by nathalie on 2006-02-16 21:05:42 as read
  • Overview of the FREEDOM compiler for mapping DSP software to FPGAs
    Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (2004), pp. 37-46.
    by D Zaretsky, M Mittal, Xiaoyong Tang, P Banerjee
    posted to arithmetic dsp for_thesis fpga fpl_paper printed xilinx by nathalie on 2006-02-10 19:29:03 as **
  • A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure
    FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 226-234.
    by SD Haynes, PYK Cheung
    posted to altera architecture arithmetic embedded for_thesis fpga fpl_paper image_processing multiplier printed xilinx by nathalie on 2006-01-10 23:48:14 as read
  • High-performance carry chains for FPGAs
    (1998), pp. 223-233.
    by Scott Hauck, Matthew M Hosler, Thomas W Fry
    posted to adder altera architecture arithmetic for_thesis fpga fpl_paper printed by nathalie on 2005-12-07 20:07:41 as ***
  • VPR and T-VPack User’s Manual, ver 4.30
    (March 2000)
    by V Betz
    posted to architecture for_thesis fpga fpl_paper packing placement printed routing by nathalie on 2005-07-20 23:56:26 as **
  • Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs
    Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 (1999), pp. 191-194.
    by SD Haynes, AB Ferrari, PYK Cheung
    posted to altera architecture arithmetic for_thesis fpga fpl_paper multiplier printed xilinx by nathalie on 2005-06-22 06:32:37 as **
  • Dynamic power consumption in Virtex&\#8482;-II FPGA family
    (2002), pp. 157-164.
    by Li Shang, Alireza S Kaviani, Kusuma Bathala
    posted to for_thesis fpga fpl_paper power power_estimation power_measurement printed xilinx by nathalie on 2005-05-13 00:09:54 as ** along with 1 person ceegrs2
  • UG073: XtremeDSP for Virtex-4 User Guide
    (4 February 2005)
    by Xilinx
    posted to arithmetic dsp for_thesis fpga fpl_paper xilinx by nathalie on 2005-05-09 23:42:16 as ***
  • A Detailed Power Model for Field-Programmable Gate Arrays
    ACM Transactions on Design Automation of Electronic Systems (TODAES)
    by KKW Poon, SJE Wilton, A Yan
    posted to for_thesis fpga fpl_paper power power_estimation printed by nathalie on 2005-05-09 19:33:27 as ***
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