The "quiet" state-a new approach to low-power multiplier design

by: N Mallios, N Burgess

Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, Vol. 2 (2003), pp. 2222-2226 Vol.2.

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Abstract

This paper proposes a novel implementation of the (4:2) redundant adder, which takes advantage of a "don't care" state to introduce a "quiet" state that suppresses glitch propagation in a multiplier's reduction tree. Simulations show that using two 32-bit random words, without Booth encoding, as much as a 10% reduction in driven capacitance can be achieved, which could translate to larger power savings due to the smaller switching activity at the adder's output wires.

@inproceedings{citeulike:880744, abstract = {This paper proposes a novel implementation of the (4:2) redundant adder, which takes advantage of a "don't care" state to introduce a "quiet" state that suppresses glitch propagation in a multiplier's reduction tree. Simulations show that using two 32-bit random words, without Booth encoding, as much as a 10\% reduction in driven capacitance can be achieved, which could translate to larger power savings due to the smaller switching activity at the adder's output wires.}, author = {Mallios, N. and Burgess, N. }, citeulike-article-id = {880744}, journal = {Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on}, keywords = {activity, arithmetic, for\_thesis, multiplier, power}, pages = {2222--2226 Vol.2}, posted-at = {2006-10-02 05:07:12}, priority = {2}, title = {The "quiet" state-a new approach to low-power multiplier design}, url = {http://ieeexplore.ieee.org/xpls/abs\_all.jsp?arnumber=1292375}, volume = {2}, year = {2003} }

RIS record

TY - CONF ID - citeulike:880744 L3 - citeulike-article-id:880744 TI - The "quiet" state-a new approach to low-power multiplier design JF - Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on VL - 2 SP - 2222 EP - 2226 Vol.2 N2 - This paper proposes a novel implementation of the (4:2) redundant adder, which takes advantage of a "don't care" state to introduce a "quiet" state that suppresses glitch propagation in a multiplier's reduction tree. Simulations show that using two 32-bit random words, without Booth encoding, as much as a 10% reduction in driven capacitance can be achieved, which could translate to larger power savings due to the smaller switching activity at the adder's output wires. KW - activity KW - arithmetic KW - for_thesis KW - multiplier KW - power AU - Mallios, N AU - Burgess, N PY - 2003/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1292375 ER -

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