Power-aware RAM Mapping for FPGA Embedded Memory Blocks

@inproceedings{Tessier, abstract = {Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21\% and overall core dynamic power can be reduced by 7\% with a minimal loss (1\%) in design performance.}, address = {New York, NY, USA}, author = {Tessier, Russell and Betz, Vaughn and Neto, David and Gopalsamy, Thiagaraja }, booktitle = {FPGA'06: Proceedings of the International Symposium on Field Programmable Gate Arrays}, citeulike-article-id = {824419}, doi = {http://dx.doi.org/10.1145/1117201.1117229}, isbn = {1595932925}, keywords = {activity, algorithms, altera, for\_thesis, fpga, logic\_synthesis, memory, power}, pages = {189--198}, posted-at = {2006-09-01 05:55:51}, priority = {2}, publisher = {ACM Press}, title = {Power-aware RAM Mapping for FPGA Embedded Memory Blocks}, url = {http://dx.doi.org/10.1145/1117201.1117229}, year = {2006} }

TY - CONF ID - Tessier L3 - citeulike-article-id:824419 TI - Power-aware RAM Mapping for FPGA Embedded Memory Blocks T2 - FPGA'06: Proceedings of the International Symposium on Field Programmable Gate Arrays SP - 189 EP - 198 AD - New York, NY, USA PB - ACM Press SN - 1595932925 N2 - Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21\% and overall core dynamic power can be reduced by 7\% with a minimal loss (1\%) in design performance. KW - activity KW - algorithms KW - altera KW - for_thesis KW - fpga KW - logic_synthesis KW - memory KW - power AU - Tessier, Russell AU - Betz, Vaughn AU - Neto, David AU - Gopalsamy, Thiagaraja PY - 2006/// UR - http://dx.doi.org/10.1145/1117201.1117229 ER -