registrieren | anmelden | FAQ      [?] 
Recent | Unread | Search | Authors | Tags | Export

kvms library [326 articles]

Neue Artikel in kvms Bibliothek.
  • The ESTEREL language
    Proceedings of the IEEE, Vol. 79, No. 9. (1991), pp. 1293-1304.
    by F Boussinot, R de Simone
    posted to sdf by kvm on 2006-10-05 22:09:45 as **
  • The SL synchronous language
    Software Engineering, IEEE Transactions on, Vol. 22, No. 4. (1996), pp. 256-266.
    by F Boussinot, R de Simone
    posted to no-tag by kvm on 2006-10-05 21:16:11 as **
  • Hierarchical compilation of macro dataflow graphs for multiprocessors with local memory
    Parallel and Distributed Systems, IEEE Transactions on, Vol. 5, No. 7. (1994), pp. 720-736.
    by Srinivasa, A Agarwal, BR Musicus
    posted to scheduling sdf by kvm on 2006-10-03 20:47:47 as **
  • Compile-time scheduling of dynamic constructs in dataflow program graphs
    Computers, IEEE Transactions on, Vol. 46, No. 7. (1997), pp. 768-778.
    by S Ha, EA Lee
    posted to scheduling sdf by kvm on 2006-10-03 20:03:40 as **
  • Communication-sensitive loop scheduling for DSP applications
    Signal Processing, IEEE Transactions on [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on], Vol. 45, No. 5. (1997), pp. 1309-1322.
    by S Tongsima, EHM Sha, NL Passos
    posted to scheduling sdf by kvm on 2006-10-03 20:02:45 as **
  • Task allocation and scheduling models for multiprocessor digital signal processing
    Acoustics, Speech, and Signal Processing [see also IEEE Transactions on Signal Processing], IEEE Transactions on, Vol. 38, No. 12. (1990), pp. 2151-2161.
    by K Konstantinides, RT Kaneshiro, JR Tani
    posted to scheduling sdf by kvm on 2006-10-03 20:01:32 as ** along with 1 person ppschedule
  • An efficient optimal task allocation and scheduling algorithm for cyclic synchronous applications
    Real-Time Computing Systems and Applications, 1999. RTCSA '99. Sixth International Conference on (1999), pp. 78-85.
    by Hee-Jun Park, Byung K Kim
    posted to scheduling sdf by kvm on 2006-10-03 19:59:38 as **
  • Memory management for dataflow programming of multirate signal processing algorithms
    Signal Processing, IEEE Transactions on [see also Acoustics, Speech, and Signal Processing, IEEE Transactions on], Vol. 42, No. 5. (1994), pp. 1190-1201.
    by SS Bhattacharyya, EA Lee
    posted to sdf by kvm on 2006-09-24 17:10:29 as **
  • Declustering: a new multiprocessor scheduling technique
    Parallel and Distributed Systems, IEEE Transactions on, Vol. 4, No. 6. (1993), pp. 625-637.
    by GC Sih, EA Lee
    posted to sdf by kvm on 2006-09-24 16:44:25 as **
  • Hierarchical static scheduling of dataflow graphs onto multiple processors
    (1995)
    by J Pino, E Lee
    posted to sdf by kvm on 2006-09-24 16:35:59 as **
  • Mapping Multiple Independent Synchronous Dataflow Graphs onto Heterogeneous Multiprocessors
    (1994)
    by J Pino, T Parks, E Lee
    posted to sdf by kvm on 2006-09-24 16:35:53 as **
  • A hierarchical multiprocessor scheduling system for DSP applications
    (1995)
    by J Pino, S Bhattacharyya, E Lee
    posted to sdf by kvm on 2006-09-24 16:34:58 as ***
  • Task assignment and scheduling under memory constraints
    Euromicro Conference, 2000. Proceedings of the 26th, Vol. 1 (2000), pp. 84-90 vol.1.
    by R Szymanek, K Kuchcinski
    posted to application-specific system-synthesis by kvm on 2006-05-03 22:41:20 as **
  • Allocation and scheduling of conditional task graph in hardware/software co-synthesis
    Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings (2001), pp. 620-625.
    by Yuan Xie, W Wolf
    posted to application-specific system-synthesis by kvm on 2006-05-03 22:40:35 as **
  • Synthesis of application specific multiprocessor architectures for process networks
    VLSI Design, 2004. Proceedings. 17th International Conference on (2004), pp. 780-783.
    by BK Dwivedi, A Kumar, M Balakrishnan
    posted to system-synthesis by kvm on 2006-05-03 21:57:01 as ** along with 1 person mperalta
  • Multiprocessor mapping of process networks: a JPEG decoding case study
    (2002), pp. 68-73.
    by EA de Kock
    posted to application-specific scheduling system-synthesis by kvm on 2006-05-02 21:43:21 as **
  • Automatic synthesis of system on chip multiprocessor architectures for process networks
    (2004), pp. 60-65.
    by Basant K Dwivedi, Anshul Kumar, M Balakrishnan
    posted to application-specific scheduling synthesis system-synthesis by kvm on 2006-05-02 21:42:03 as **
  • Reducing the complexity of ILP formulations for synthesis
    (1997), pp. 58-64.
    by Anne Mignotte, Olivier Peyran
    posted to integer-linear-programming scheduling by kvm on 2005-12-19 19:25:18 as **
  • A complete compiler approach to auto-parallelizing C programs for multi-DSP systems
    Parallel and Distributed Systems, IEEE Transactions on, Vol. 16, No. 3. (2005), pp. 234-245.
    by B Franke, MFP O'Boyle
    posted to parallelization by kvm on 2005-11-21 15:09:58 as **
  • Translating imperative affine nested loop programs into process networks
    (2002), pp. 89-111.
    by Ed F Deprettere, Edwin Rijpkema, Bart Kienhuis
    posted to memory synthesis by kvm on 2005-10-31 21:42:35 as **
  • Quantitative characterization of event streams in analysis of hard real-time applications
    Real-Time and Embedded Technology and Applications Symposium, 2004. Proceedings. RTAS 2004. 10th IEEE (2004), pp. 450-459.
    by E Wandeler, A Maxiaguine, L Thiele
    posted to memory synthesis by kvm on 2005-10-31 21:18:04 as **
  • Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms
    Design & Test of Computers, IEEE, Vol. 21, No. 5. (2004), pp. 368-377.
    by A Maxiaguine, S Kunzli, L Thiele, S Chakraborty
    posted to compiler scheduling by kvm on 2005-10-31 21:15:23 as **
  • Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms
    by Alexander
    posted to compiler scheduling by kvm on 2005-10-31 21:14:07 as **
  • Rate Analysis for Streaming Applications with On-chip Buffer Constraints
    by Alexander Maxiaguine, Et
    posted to memory synthesis by kvm on 2005-10-16 19:02:18 as **
  • Integer programming
    posted to integer-linear-programming by kvm on 2005-10-06 02:11:04 as **
  • Space-time scheduling of instruction-level parallelism on a raw machine
    SIGPLAN Not., Vol. 33, No. 11. (November 1998), pp. 46-57.
    by Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe
    posted to compiler scheduling by kvm on 2005-09-20 14:57:40 as **
  • Stage scheduling: a technique to reduce the register requirements of a modulo schedule
    (1995), pp. 338-349.
    by Alexandre E Eichenberger, Edward S Davidson
    posted to compiler moduloscheduling vliw by kvm on 2005-09-20 14:56:42 as read
  • Swing Modulo Scheduling: A Lifetime-Sensitive Approach
    (1996)
    by Josep Llosa
    posted to compiler moduloscheduling vliw by kvm on 2005-09-20 14:56:02 as **
  • Synthesis of custom processors based on extensible platforms
    (2002), pp. 641-648.
    by Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K Jha
    posted to application-specific computer-architecture synthesis by kvm on 2005-09-20 14:55:19 as **
  • Synthesis of application specific instructions for embedded DSP software
    (1998), pp. 665-671.
    by Hoon Choi, Seung H Hwang, Chong-Min Kyung, In-Cheol Park
    posted to synthesis vliw by kvm on 2005-09-20 14:53:38 as **
  • Synthesis of application-specific memory designs
    IEEE Trans. Very Large Scale Integr. Syst., Vol. 5, No. 1. (March 1997), pp. 101-111.
    by Herman Schmit, Donald E Thomas
    posted to memory synthesis by kvm on 2005-09-20 14:52:39 as **
  • The MIMOLA design system a computer aided digital processor design method
    (1979), pp. 53-58.
    by G Zimmermann
    posted to adl synthesis by kvm on 2005-09-17 20:37:57 as **
  • The Multicluster Architecture: Reducing Cycle Time Through Partitioning
    (1997), pp. 149-159.
    by Keith I Farkas, Paul Chow, Norman P Jouppi, Zvonko G Vranesic
    posted to clustering computer-architecture vliw by kvm on 2005-09-17 20:37:20 as **
  • The Multiflow Trace Scheduling Compiler
    The Journal of Supercomputing, Vol. 7, No. 1-2. (1993), pp. 51-142.
    by Geoffrey P Lowney, Stefan M Freudenberger, Thomas J Karzes, WD Lichtenstein, Robert P Nix, John S O'Donnell, John C Ruttenberg
    posted to compiler vliw by kvm on 2005-09-17 20:36:48 as ** along with 2 people damaru ronnix
  • The Omega test: a fast and practical integer programming algorithm for dependence analysis
    (1991), pp. 4-13.
    by William Pugh
    posted to compiler integer-linear-programming parallelization scheduling by kvm on 2005-09-17 20:36:21 as ** along with 4 people and 1 group jolilius pmatos mzygmunt pirapira TUCS-ES_Lab
  • The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
    IEEE Micro, Vol. 22, No. 2. (March 2002), pp. 25-35.
    by Michael B Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, Anant Agarwal
    posted to compiler computer-architecture fpga by kvm on 2005-09-17 20:35:42 as **
  • The superblock: an effective technique for VLIW and superscalar compilation
    J. Supercomput., Vol. 7, No. 1-2. (1993), pp. 229-248.
    by Wen-Mei W Hwu, Scott A Mahlke, William Y Chen, Pohua P Chang, Nancy J Warter, Roger A Bringmann, Roland G Ouellette, Richard E Hank, Tokuzo Kiyohara, Grant E Haab, John G Holm, Daniel M Lavery
    posted to compiler vliw by kvm on 2005-09-17 20:32:10 as ** along with 1 person visit0r
  • The design of a high performance low power microprocessor
    (1996), pp. 11-16.
    by Dan Dobberpuhl
    posted to computer-architecture low-power by kvm on 2005-09-17 20:30:56 as **
  • The effect of reconfigurable units in superscalar processors
    (2001), pp. 141-150.
    by Jorge E Carrillo, Paul Chow
    posted to computer-architecture fpga by kvm on 2005-09-17 20:30:24 as **
  • The performance potential of data dependence speculation & collapsing
    (1996), pp. 238-247.
    by Yiannakis Sazeides, Stamatis Vassiliadis, James E Smith
    posted to computer-architecture by kvm on 2005-09-17 20:29:43 as **
  • The Transmogrifier C hardware description language and compiler for FPGAs
    (1995)
    by D Galloway
    posted to adl compiler fpga hdl by kvm on 2005-09-17 20:29:00 as ** along with 1 person ronnix
  • Theory of Linear and Integer Programming
    (04 June 1998)
    by Alexander Schrijver
    posted to book integer-linear-programming linear-programming math by kvm on 2005-09-17 20:27:03 as **
  • Trace scheduling: a technique for global microcode compaction
    (1995), pp. 186-198.
    by Joseph A Fisher
    posted to compiler scheduling by kvm on 2005-09-17 20:26:03 as **
  • Using Lightweight Procedures to Improve Instruction Cache Performance
    No. CS-TR-1999-1390. (1999)
    by Krishna Kunchithapadam, James R Larus
    posted to cache computer-architecture by kvm on 2005-09-17 20:24:46 as **
  • Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures
    (1998), pp. 308-315.
    by Emre &\#214;zer, Sanjeev Banerjia, Thomas M Conte
    posted to clustering compiler scheduling by kvm on 2005-09-17 14:28:13 as **
  • Xtensa: A Configurable and Extensible Processor
    IEEE Micro, Vol. 20, No. 2. (March 2000), pp. 60-70.
    by RE Gonzalez
    posted to architecture reconfigurable by kvm on 2005-09-17 14:23:59 as **
  • Xtensa Architecture and Performance
    (September 2002)
    posted to architecture reconfigurable by kvm on 2005-09-17 14:23:59 as **
  • Will Physical Scalability Sabotage Performance Gains
    IEEE Computer, Vol. 30, No. 9. (September 1997), pp. 37-39.
    by D Matzke
    posted to analysis architecture by kvm on 2005-09-17 14:23:59 as **
  • Very Long Instruction Word Architectures and the ELI-52
    (1983), pp. 140-150.
    by J Fisher
    posted to compiler vliw by kvm on 2005-09-17 14:23:59 as **
  • Variable Partitioning for Dual Memory Bank DSPs
    (May 2001), pp. 1121-1124.
    by Rainer Leupers, Daniel Kotte
    posted to architecture compiler by kvm on 2005-09-17 14:23:59 as **
    • Bemerkung: Sie können diese Seite wie folgt zitieren: http://www.citeulike.org/user/kvm

    Result page: 1 2 3 4 5 6 7 Next RIS BibTeX
    CiteULike organises scholarly (or academic) papers or literature and provides bibliographic (which means it makes bibliographies) for universities and higher education establishments. It helps undergraduates and postgraduates. People studying for PhDs or in postdoctoral (postdoc) positions. The service is similar in scope to EndNote or RefWorks or any other reference manager like BibTeX, but it is a social bookmarking service for scientists and humanities researchers.